Low-Power 9T Subthreshold SRAM Cell with Single-Ended Write Scheme

Demand for low power circuits is increasing and an easy way to meet low power requirement is to scale down the supply voltage. When the power supply is less than the threshold voltage of the transistors, the circuit is said to be operating in the subthreshold region. This work presents a novel 9T subthreshold SRAM cell. Some important features of the proposed design are employment of single-ended write scheme and differential sensing scheme for read operation. Another important highlight of the proposed design is the use of stack transistor in the left part of the cross-coupled inverter. Stacking leads to substantial reduction in leakage current. The proposed design has been compared to the previously proposed conventional 9T SRAM cell. It is observed that the proposed design shows 1.95x improvement in read access time and 1.94x improvement in leakage current as compared to the conventional 9T SRAM cell at a supply voltage of 300 mV. Also, there is 5.5% improvement in hold power and 1.67x improvement in hold power variability at V-DD = 300 mV. The simulation tool used for estimation of the parameters is Synopsys' HSPICE.