Asymmetrical Write-Assist for Single-Ended SRAM Operation

被引：0

作者：

Lin, Jihi-Yu ^{[1
]}

Tu, Ming-Hsien ^{[1
]}

Tsai, Ming-Chien ^{[1
]}

Jou, Shyh-Jye ^{[1
]}

Chuang, Ching-Te ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu, Taiwan

来源：

IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2009年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, asymmetrical Write-assist cell virtual ground biasing and positive feedback sensing keeper schemes are proposed to improve the Read Static Noise Margin (RSNM), Write Margin (WM), and operation speed of a single-ended Read/Write 8T SRAM cell. A 4Kbit SRAM implemented in 90nm CMOS technology achieves 1uW/bit average power consumption at 6MHz, V-min of 410mV at 6MHz, and 234MHz maximum operation frequency at 600mV.

引用

页码：101 / 104

页数：4

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