A single-chip MPEG-2 422P@ML video, audio, and system encoder with a 162 MHz media-processor core and dual motion estimation cores

被引:0
|
作者
Matsumura, T [1 ]
Kumaki, S
Segawa, H
Ishihara, K
Hanami, A
Matsuura, Y
Scotzniovsky, S
Takata, H
Yamada, A
Murayama, S
Wada, T
Ohira, H
Shimada, T
Asano, K
Yoshida, T
Yoshimoto, M
Tsuchihashi, K
Horiba, Y
机构
[1] Mitsubishi Elect Corp, Syst LSI Dev Ctr, Itami, Hyogo 6648641, Japan
[2] Mitsubishi Elect Corp, Informat Technol R&D Ctr, Kamakura, Kanagawa 2478501, Japan
[3] Mitsubishi Elect Corp, Itami, Hyogo 6648641, Japan
关键词
video encoder; MPED-2; media-processor; audio encoder; system encoder; motion estimation;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A single-chip MPEG-2 video, audio and system encoder LSI has been developed. It performs concurrent real-time processing of MPEG-2 422P@ML video encoding. 2- channel Dolby Digital or MPEG-1 audio encoding, and system encoding that generates a multiplexed transport stream (TS) or a program stream (PS). Advanced hybrid architecture, which combines a high performance VLIW media-processor D30V and hard-wired video processing circuits has been adopted to satisfy the demands of both high flexibility and enormous computational capability. A unified control scheme has been newly proposed that hierarchically manages adaptive task priority control over asynchronous video, audio, and system encoding processes in order to achieve real-time concurrent processing using a single D30V. Dual dedicated motion estimation cores consisting of a coarse ME core (CME) for wide range searches and a fine ME core (FME) for precise searches have been integrated to produce high picture quality while using a small amount of hardware. Adopting these features, a single-chip encoder has been fabricated using 0.25-micron 4-layer metal CMOS technology, and integrated into a 14.2 mm x 14.2 mm die with 11 million transistors.
引用
收藏
页码:108 / 122
页数:15
相关论文
共 14 条
  • [1] A single-chip MPEG2 422@ML video, audio, and system encoder with a 162-MHz media-processor and dual motion estimation cores
    Kumaki, S
    Matsumura, T
    Ishihara, K
    Segawa, H
    Kawamoto, K
    Ohira, H
    Shimada, T
    Sato, H
    Hattori, T
    Wada, T
    Honma, H
    Watanabe, T
    Sato, H
    Asano, K
    Yoshida, T
    [J]. PROCEEDINGS OF THE IEEE 1999 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 1999, : 95 - 98
  • [2] Single-chip MPEG2 422ML video, audio, and system encoder with a 162-MHz media-processor and dual motion estimation cores
    Kumaki, Satoshi
    Matsumura, Tetsuya
    Ishihara, Kazuya
    Segawa, Hiroshi
    Kawamoto, Kiyofumi
    Ohira, Hideo
    Shimada, Toshiaki
    Sato, Hidenori
    Hattori, Takashi
    Wada, Tetsuro
    Honma, Hiroshi
    Watanabe, Tetsuya
    Sato, Hisakazu
    Asano, Ken-ichi
    Yoshida, Toyohiko
    [J]. Proceedings of the Custom Integrated Circuits Conference, 1999, : 95 - 98
  • [3] A 99-mm2 0.7-w single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mb embedded DRAM for portable 422P@HL encoder system
    Kumaki, S
    Takata, H
    Ajioka, Y
    Ooishi, T
    Ishihara, K
    Hanami, A
    Tsuji, T
    Watanabe, T
    Morishima, C
    Yoshizawa, T
    Sato, H
    Hattori, S
    Koshio, A
    Tsukamoto, K
    Matsumura, T
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2002, 37 (03) : 450 - 454
  • [4] A 99-mm2, 0.7-W, single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mbit embedded DRAM for portable 422P@HL encoder system
    Kumaki, S
    Takata, H
    Ajioka, Y
    Ooishi, T
    Ishihara, K
    Hanami, A
    Tsuji, T
    Kanehira, Y
    Watanabe, T
    Morishima, C
    Yoshizawa, T
    Sato, H
    Hattori, S
    Koshio, A
    Tsukamoto, K
    Matsumura, T
    [J]. PROCEEDINGS OF THE IEEE 2001 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2001, : 425 - 428
  • [5] A single-chip MPEG-2 MP@ML audio/video encoder/decoder with a programmable Video Interface Unit
    Chen, CT
    Chen, TC
    Jeng, FC
    Cheng, H
    Konstantinides, K
    [J]. 2001 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS I-VI, PROCEEDINGS: VOL I: SPEECH PROCESSING 1; VOL II: SPEECH PROCESSING 2 IND TECHNOL TRACK DESIGN & IMPLEMENTATION OF SIGNAL PROCESSING SYSTEMS NEURALNETWORKS FOR SIGNAL PROCESSING; VOL III: IMAGE & MULTIDIMENSIONAL SIGNAL PROCESSING MULTIMEDIA SIGNAL PROCESSING - VOL IV: SIGNAL PROCESSING FOR COMMUNICATIONS; VOL V: SIGNAL PROCESSING EDUCATION SENSOR ARRAY & MULTICHANNEL SIGNAL PROCESSING AUDIO & ELECTROACOUSTICS; VOL VI: SIGNAL PROCESSING THEORY & METHODS STUDENT FORUM, 2001, : 941 - 944
  • [6] An embedded software scheme for a real-time single-chip MPEG-2 encoder system with a VLIW media processor core
    Segawa, H
    Matsuura, Y
    Kumaki, S
    Matsumura, T
    Scotzniovsky, S
    Murayama, S
    Wada, T
    Harada, A
    Ohara, E
    Asano, K
    Yoshida, T
    Horiba, Y
    [J]. IEICE TRANSACTIONS ON ELECTRONICS, 2001, E84C (02) : 202 - 211
  • [7] A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking
    Mizuno, M
    Ooi, Y
    Hayashi, N
    Goto, J
    Hozumi, M
    Furuta, K
    Shibayama, A
    Nakazawa, Y
    Ohnishi, O
    Zhu, SY
    Yokoyama, Y
    Katayama, Y
    Takano, H
    Miki, N
    Senda, Y
    Tamitani, I
    Yamashina, M
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (11) : 1807 - 1816
  • [8] 1.5-W single-chip MPEG-2 MPML video encoder with low power motion estimation and clocking
    NEC Corp, Kanagawa, Japan
    [J]. IEEE J Solid State Circuits, 11 (1807-1816):
  • [9] Motion estimation and compensation hardware architecture for a scene-adaptive algorithm on a single-chip MPEG-2 video encoder
    Nitta, K
    Minami, T
    Kondo, T
    Ogura, T
    [J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2001, E84D (03) : 317 - 325
  • [10] Motion estimation and compensation hardware architecture for a scene-adaptive algorithm on a single-chip MPEG-2 video encoder
    Nitta, Koyo
    Minami, Toshihiro
    Kondo, Toshio
    Ogura, Takeshi
    [J]. 2001, Institute of Electronics, Information and Communication, Engineers, IEICE (E84-D)