Nanoscale epitaxial cobalt salicide bitlines for charge trapping memory cells

被引:1
|
作者
Kleint, C. A. [1 ]
Mueller, T. [1 ]
Teichert, S. [1 ]
Fitz, C. [1 ]
Nagel, N. [1 ]
Kuesters, K. H. [1 ]
机构
[1] Qimonda Dresden GmbH & Co, OHG, D-01099 Dresden, Germany
关键词
D O I
10.1063/1.2906366
中图分类号
O59 [应用物理学];
学科分类号
摘要
An epitaxial CoSi2 process is presented, which allows the self-aligned formation of bitlines with only a few tens of nanometer width for Twin Flash memory cells in the 63 nm generation. The bitlines show a good thermal stability and low resistance for widths down to 35 nm, where polycrystalline CoSi2 is known to exhibit a strong narrow linewidth effect. Transmission electron microscopy studies revealed a cube-on-cube epitaxy with only a few twins depending on the annealing conditions. The low bitline resistance results in a linear drain voltage dependence of the programing characteristics and a suppression of secondary electron injection during programing. (C) 2008 American Institute of Physics.
引用
收藏
页数:3
相关论文
共 50 条
  • [21] Metallic Source/Drain Ge-Based Charge-Trapping Memory Cells
    Chen, Yu-Hsuan
    Shih, Chun-Hsing
    Teng, Hung-Jin
    Lien, Chenhsin
    2019 SILICON NANOELECTRONICS WORKSHOP (SNW), 2019, : 59 - 60
  • [22] Improved Operation Characteristics for Nonvolatile Charge-Trapping Memory Capacitors with High-κ Dielectrics and SiGe Epitaxial Substrates
    侯朝昭
    王桂磊
    项金娟
    姚佳欣
    吴振华
    张青竹
    殷华湘
    Chinese Physics Letters, 2017, 34 (09) : 101 - 105
  • [23] Improved Operation Characteristics for Nonvolatile Charge-Trapping Memory Capacitors with High-κ Dielectrics and SiGe Epitaxial Substrates
    Hou, Zhao-Zhao
    Wang, Gui-Lei
    Xiang, Jin-Juan
    Yao, Jia-Xin
    Wu, Zhen-Hua
    Zhang, Qing-Zhu
    Yin, Hua-Xiang
    CHINESE PHYSICS LETTERS, 2017, 34 (09)
  • [24] Bifunctional Nanoscale Assemblies: Multistate Electrochromics Coupled with Charge Trapping and Release
    Hamo, Yonatan
    Lahav, Michal
    van der Boom, Milko E.
    ANGEWANDTE CHEMIE-INTERNATIONAL EDITION, 2020, 59 (07) : 2612 - 2617
  • [25] Modelling of Reliability of nanoscale MOSFETs within the Discrete Charge Trapping Paradigm
    Adamu-Lema, Pikru
    Amoroso, Salvatore M.
    Gerrer, Louis
    Asenov, Asen
    2013 14TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (ULIS), 2013, : 154 - 157
  • [26] ZnO Based Charge Trapping Memory with Embedded Nanoparticles
    Rizk, Ayman
    Oruc, Feyza B.
    Okyay, Ali K.
    Nayfeh, Ammar
    2012 12TH IEEE CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO), 2012,
  • [27] Research on charge trapping memory's over erase
    Wang Jia-Yu
    Dai Yue-Hua
    Zhao Yuan-Yang
    Xu Jian-Bin
    Yang Fei
    Dai Guang-Zhen
    Yang Jin
    ACTA PHYSICA SINICA, 2014, 63 (20)
  • [28] New nonvolatile memory with charge-trapping sidewall
    Fukuda, M
    Nakanishi, T
    Nara, Y
    IEEE ELECTRON DEVICE LETTERS, 2003, 24 (07) : 490 - 492
  • [29] Local Accumulated Free Carriers in Charge Trapping Memory
    Song, Y. C.
    Liu, X. Y.
    Zhao, K.
    Kang, J. F.
    Han, R. Q.
    Xia, Z. L.
    Kim, D.
    Lee, K-H
    2008 IEEE SILICON NANOELECTRONICS WORKSHOP, 2008, : 185 - +
  • [30] Influence of Nanoscale Charge Trapping Layer on the Memory and Synaptic Characteristics of a Novel Rubidium Lead Chloride Quantum Dot Based Memristor
    Das, Ujjal
    Sarkar, Pranab Kumar
    Das, Dip
    Paul, Bappi
    Roy, Asim
    ADVANCED ELECTRONIC MATERIALS, 2022, 8 (05):