A Co-Design Method for Parallel Image Processing Accelerator based on DSP and FPGA

被引：2
|
作者：
Wang, Ze [1 ]
Weng, Kaijian [1 ]
Cheng, Zhao [2 ]
Yan, Luxin [1 ]
Guan, Jing [1 ]
机构：
[1] Huazhong Univ Sci & Technol, State Key Lab Multispectral Informat Proc Technol, Inst Pattern Recognit & AI, Wuhan 430074, Peoples R China
[2] CAST, Inst Manned Space Syst Engn, Beijing 100094, Peoples R China
来源：
MIPPR 2011: PARALLEL PROCESSING OF IMAGES AND OPTIMIZATION AND MEDICAL IMAGING PROCESSING | 2011年 / 8005卷
基金：
中国国家自然科学基金;
关键词：
Image processing accelerator; co-design method; parallel architecture; coprocessor;
D O I：
10.1117/12.901244
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, we present a co-design method for parallel image processing accelerator based on DSP and FPGA. DSP is used as application and operation subsystem to execute the complex operations, and in which the algorithms are resolving into commands. FPGA is used as co-processing subsystem for regular data-parallel processing, and operation commands and image data are transmitted to FPGA for processing acceleration. A series of experiments have been carried out, and up to a half or three quarter time is saved which supports that the proposed accelerator will consume less time and get better performance than the traditional systems.
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收藏
页数：6
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