A Co-Design Method for Parallel Image Processing Accelerator based on DSP and FPGA

被引：2
|
作者：
Wang, Ze [1 ]
Weng, Kaijian [1 ]
Cheng, Zhao [2 ]
Yan, Luxin [1 ]
Guan, Jing [1 ]
机构：
[1] Huazhong Univ Sci & Technol, State Key Lab Multispectral Informat Proc Technol, Inst Pattern Recognit & AI, Wuhan 430074, Peoples R China
[2] CAST, Inst Manned Space Syst Engn, Beijing 100094, Peoples R China
来源：
MIPPR 2011: PARALLEL PROCESSING OF IMAGES AND OPTIMIZATION AND MEDICAL IMAGING PROCESSING | 2011年 / 8005卷
基金：
中国国家自然科学基金;
关键词：
Image processing accelerator; co-design method; parallel architecture; coprocessor;
D O I：
10.1117/12.901244
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, we present a co-design method for parallel image processing accelerator based on DSP and FPGA. DSP is used as application and operation subsystem to execute the complex operations, and in which the algorithms are resolving into commands. FPGA is used as co-processing subsystem for regular data-parallel processing, and operation commands and image data are transmitted to FPGA for processing acceleration. A series of experiments have been carried out, and up to a half or three quarter time is saved which supports that the proposed accelerator will consume less time and get better performance than the traditional systems.
引用
收藏
页数：6
相关论文
共 50 条
  • [41] The Design of MIPI Image Processing Based on FPGA
    Wang, Zhanchao
    Huang, Min
    Zhang, Guifeng
    Qian, Lulu
    OPTICAL SENSORS 2019, 2019, 11028
  • [42] Design of Image Acquisition and Processing Based on FPGA
    Li, Chao
    Zhang, Yu-lin
    Zheng, Zhao-na
    2009 INTERNATIONAL FORUM ON INFORMATION TECHNOLOGY AND APPLICATIONS, VOL 3, PROCEEDINGS, 2009, : 113 - 115
  • [43] An Intelligent Interface Design Method Based on DSP and FPGA
    Chi, Zhiyou
    Jia, Qingzhong
    Wang, Xingdou
    Liu, Zongrui
    Wu, Ping
    Proceedings of the 2016 International Conference on Electrical, Mechanical and Industrial Engineering (ICEMIE), 2016, 51 : 318 - 321
  • [44] Co-design for speed and space optimization of chips for image processing
    Kaszubiak, J.
    Tornow, M.
    Michaelis, B.
    Szczepanski, T.
    PROCEEDINGS OF THE SIXTH IASTED INTERNATIONAL CONFERENCE ON MODELLING, SIMULATION, AND OPTIMIZATION: SCIENCE AND TECHNOLOGY FOR DEVELOPMENT IN THE 21ST CENTURY, 2006, : 19 - +
  • [45] Design of Image Acquisition and Transmission System Based on DSP and FPGA
    Zhang, Peng
    Zhong, Jun
    Guo, An-ming
    Peng, Qiang
    2011 INTERNATIONAL CONFERENCE ON COMPUTATIONAL SCIENCE AND APPLICATIONS, 2011, : 62 - 67
  • [46] DSP-Based Parallel Processing Model of Image Rotation
    Zhang Shuang
    Jin Gang
    Qin Yu-ping
    CEIS 2011, 2011, 15
  • [47] Macro-processing Based SoC SW/HW Co-design Method
    Zhi, Zhao Hong
    PROCEEDINGS OF 2010 CROSS-STRAIT CONFERENCE ON INFORMATION SCIENCE AND TECHNOLOGY, 2010, : 66 - 71
  • [48] Sparse-YOLO: Hardware/Software Co-Design of an FPGA Accelerator for YOLOv2
    Wang, Zixiao
    Xu, Ke
    Wu, Shuaixiao
    Liu, Li
    Liu, Lingzhi
    Wang, Dong
    IEEE ACCESS, 2020, 8 : 116569 - 116585
  • [49] Efficient HW/SW Co-design of FPGA Accelerator to Detect Anomaly Attacks in Smart Grids
    Liu, Hongsen
    Liu, Guangyi
    Li, Shizhong
    Meng, Wenchao
    Wang, Lin
    Sun, Yong
    2024 33RD INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS, ISIE 2024, 2024,
  • [50] Toward Efficient Co-Design of CNN Quantization and HW Architecture on FPGA Hybrid-Accelerator
    Zhang, Yiran
    Li, Guiying
    Yuan, Bo
    2024 INTERNATIONAL SYMPOSIUM OF ELECTRONICS DESIGN AUTOMATION, ISEDA 2024, 2024, : 678 - 683
12345