High throughput floating-point dividers implemented in FPGA

被引：7
|
作者：
Malik, Peter [1 ]
机构：
[1] Slovak Acad Sci, Inst Informat, Dubravska Cesta 9, Bratislava 84507, Slovakia
来源：
2015 IEEE 18TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS 2015) | 2015年
关键词：
D O I：
10.1109/DDECS.2015.66
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
New high throughput floating-point dividers implemented in FPGA based on different fast computation division algorithms are proposed. The hardware implementations uses 32-bit floating-point single precision. The implementations include both multiplicative inverse and division. The proposed hardware implementations are designed with high computation speed and throughput. They are oriented for high computation demanding applications with multiple division computations in short sequences.
引用
收藏
页码：291 / 294
页数：4
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