A universal delay line circuit for variation resilient IC with self-calibrated time-to-digital converter

被引：0

作者：

Shao, Shuai ^{[1
]}

Shi, Youhua ^{[2
]}

Dai, Wentao ^{[1
]}

Meng, Jianyi ^{[3
]}

Shan, Weiwei ^{[1
]}

机构：

[1] Southeast Univ, Natl ASIC Syst & Res Engn Ctr, Nanjing, Jiangsu, Peoples R China

[2] Waseda Univ, Waseda Adv Res Inst, Tokyo, Japan

[3] Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China

来源：

PROCEEDINGS OF THE 2015 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC) | 2015年

关键词：

Adaptive voltage scaling; variation resilient; universal delay monitor; time -to-digital converter;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A universal delay monitor used to imitate the real critical paths is developed for variation resilient integrated circuit. This monitor is constructed based on the different proportion of logic cells and interconnects. The delay of the monitor is detected by a time-to-digital converter which keeps the sampling results precise. To reduce the deviation of the sampling results caused by PVT, a novel time-to-digital converter with self-calibration mechanism is developed. This variation resilient method based adaptive voltage scaling is applied on an ARM7 based System on a Chip on 0.18 mu m CMOS process with a 112M signoff frequency and an area of 1.3*1.3 mm(2). The simulation results show that it has a 43.42% gain of power consumption under FF corner, -25 degrees Ccompared to the fixed 1.8 V traditional design.

引用

页码：126 / 129

页数：4

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