Electrical modeling and simulation challenges in chip-package codesign

被引：11
|
作者：
Cangellaris, AC [1 ]
机构：
[1] Univ Illinois, Dept Elect & Comp Engn, Urbana, IL 61801 USA
来源：
IEEE MICRO | 1998年 / 18卷 / 04期
关键词：
D O I：
10.1109/40.710871
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
High-performance, multifunctional systems demand novel, often revolutionary, practices in functional-block integration and packaging. Independent chip, package, and board design will have to give way to a holistic approach.
引用
收藏
页码：50 / 59
页数：10
相关论文
共 50 条
  • [31] Chip-package interaction (CPI): An industry perspective
    Ray, Urmi
    Advancing Microelectronics, 2017, 44 (06):
  • [32] Chip-Package Hierarchical Power Distribution Network Modeling and Analysis Based on a Segmentation Method
    Kim, Jaemin
    Lee, Woojin
    Shim, Yujeong
    Shim, Jongjoo
    Kim, Kiyeong
    Pak, Jun So
    Kim, Joungho
    IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2010, 33 (03): : 647 - 659
  • [33] Design and Modeling of Monolithic Integrated Millimeterwave Chip-Package Antennas and Wireless Communication Links
    Russer, J.
    Mukhtar, F.
    Wane, S.
    Bajon, D.
    Russer, P.
    2012 IEEE ASIA-PACIFIC CONFERENCE ON ANTENNAS AND PROPAGATION (APCAP), 2012, : 211 - +
  • [34] A novel simulation methodology for full chip-package thermo-mechanical reliability investigations
    Karunamurthy, Balamurugan
    Ostermann, Thomas
    Bhattacharya, Monojit
    Maity, Sandipan
    MICROELECTRONICS JOURNAL, 2014, 45 (07) : 966 - 971
  • [35] Novel Methodology for Assessing Chip-Package Interaction Effects on Chip Performance
    Kteyan, Armen
    Choy, Jun-Ho
    Sukharev, Valeriy
    Bertoletti, Massimo
    Maiorca, Carmelo
    Zadra, Rossana
    Inzaghi, Massimo
    Gattere, Gabriele
    Zinco, Giancarlo
    Valente, Paolo
    Bardelli, Roberto
    Valerio, Alessandro
    Rolandi, Pierluigi
    Monetti, Mattia
    Cuomo, Valentina
    Santapa, Salvatore
    ISPD'22: PROCEEDINGS OF THE 2022 INTERNATIONAL SYMPOSIUM ON PHYSICAL DESIGN, 2022, : 83 - 89
  • [36] A Broadband Chip-Level Power-Bus Model Feasible for Power Integrity Chip-Package Codesign in High-Speed Memory Circuits
    Chuang, Hao-Hsiang
    Hsu, Chih-Jung
    Hong, Jacky
    Yu, Chun-Huang
    Cheng, Argy
    Ku, Joseph
    Wu, Tzong-Lin
    IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, 2010, 52 (01) : 235 - 239
  • [37] Adaptive chip-package thermal analysis for synthesis and design
    Yang, Yonghong
    Gu, Zhenyu
    Zhu, Changyun
    Shang, Li
    Dick, Robert P.
    2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS, 2006, : 842 - +
  • [38] Evaluation of Chip-Package Interaction by Means of Stress Sensors
    Sun, Jingyao
    Gabani, Dhruvit
    Silber, Christian
    Dietz, Franz
    Kabakchiev, Alexander
    Gromala, Przemyslaw
    Thewes, Roland
    Pecanac, Goran
    IEEE SENSORS JOURNAL, 2022, 22 (13) : 12959 - 12966
  • [39] Analysis of the effect of AC noise on DC bias of VGA for UHF RFID using chip-package co-modeling and simulation
    Le, Hyein
    Shim, Yujeong
    Park, Hyungjeong
    Ryu, Chunghyun
    Yoon, Changwook
    Kim, Joungho
    2007 9TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, VOLS 1 AND 2, 2007, : 591 - 594
  • [40] Modeling and parameter extraction methods of bond-wires for chip-package co-design
    Jing, Weiping
    Sun, Ling
    Sun, Haiyan
    ICEPT: 2006 7TH INTERNATIONAL CONFERENCE ON ELECTRONICS PACKAGING TECHNOLOGY, PROCEEDINGS, 2006, : 173 - +
12345