Low power CMOS logic families

被引：0

作者：

Allam, MW ^{[1
]}

Elmasry, MI ^{[1
]}

机构：

[1] Univ Waterloo, VLSI Res Grp, Waterloo, ON N2L 3G1, Canada

来源：

1998 MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS | 1999年

关键词：

D O I：

10.1109/MWSCAS.1998.759520

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Low power design is the key for wireless communication devices and portable computing systems. Many logic families are suggested as candidates for low power design. In this paper; we compare four famous logic families as candidates for low power and high performance logic circuits. The comparisons are based on power, delay and interference produced. A 16 bit Carry Look Ahead adder is used to compare the performance of the four logic families at different operating conditions.

引用

页码：419 / 422

页数：4

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