A 35-to-46-Gb/s ultra-low jitter clock and data recovery circuit for optical fiber transmission systems

We demonstrated an ultra-low jitter clock and data recovery circuit that covers an ultra wide frequency range from 35 Gb/s to 46 Gb/s. Our CDR has a newly developed dual input LC-VCO with a fine/coarse tuning scheme and a dual-loop architecture [1], which consists of a phase tracking loop and a frequency tracking loop. The CDR chip, which was made using an InP-HBT process, shows an extremely clear eye opening with an ultra-low jitter (< 9 mUI-rms) and an error-free operation (<1x10(-12)) throughout a wide range of 35 to 46 Gb/s at a 2(31)-1 PRBS signal. The RMS and peak-to-peak jitter of the recovered clock were 226 A and 1.56 ps, respectively. We suppressed output jitter to half of that found in previous work [2]. In addition, a stable bit error rate (BER) that is insensitive to PRBS word length was demonstrated during an optical transmission test. These results show that our full-rate CDR is a very promising chip for 40-Gb/s-class optical transmission systems with the multi data rates.