A statistical gate-delay model considering intra-gate variability

被引:0
|
作者
Okada, K [1 ]
Yamaoka, K [1 ]
Onodera, H [1 ]
机构
[1] Kyoto Univ, Dept Commun & Comp Engn, Kyoto, Japan
来源
ICCAD-2003: IEEE/ACM DIGEST OF TECHNICAL PAPERS | 2003年
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper proposes a model for calculating statistical gate-delay variation caused by intra-chip and inter-chip variability. As the variation of individual gate delays directly influences the circuit-delay variation, it is important to characterize each gate-delay variation accurately. Furthermore, as every transistor in a gate affects the transient characteristics of the gate, it is also necessary to consider the intra-gate variability in the model of gate-delay variation. This effect is not captured in existing statistical delay analyses. The proposed model considers the intra-gate variability through the introduction of sensitivity constants. The accuracy of the model is evaluated, and some simulation results for circuit delay variation are presented.
引用
收藏
页码:908 / 913
页数:6
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