An Analytical Gate Delay Variability Model for Low-Power and Low-Voltage Applications

Understanding the timing characteristics behavior, such as the logic gate delay, is an essential task in ICs. In low-power and low-voltage devices, due to their high sensitivity and slope propagation, time-dependent sources of variability (e.g., the bias temperature instability) become more significant, affecting time delay variability. In this context, an improved analytical model to properly account for CMOS logic gate delay propagation and its variability is presented, taking into account how low-power devices' properties impact the analysis. The derived model shows a good estimative for the parameters' degradation. Supported by Monte Carlo simulations, the technique reduced the gate delay approximation errors by close to 50% when compared to simplified methods with the same objective.