Reconfigurable threshold logic gates with nanoscale DG-MOSFETs

被引:2
|
作者
Kaya, Savas [1 ]
Harned, Hesham F. A.
Ting, Darwin T.
Creech, Gregory
机构
[1] Ohio Univ, Rush Coll Engn & Technol, Sch Elect Engn & Comp Sci, Athens, OH 45701 USA
[2] WPAFB, Air Force Res Lab Dayton, Sensors Directorate, Wright Patterson AFB, OH 45433 USA
关键词
threshold logic; double-gate MOSFETs; SOI; reconfigurable logic systems;
D O I
10.1016/j.sse.2007.08.011
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The benefits in using double-gate (DG) MOSFETs as components of threshold logic gates (TLG) have been analyzed for the first time. A novel, variable-weight DG-TLG has also been proposed, which can greatly widen the range of reconfigurable functions accessible to users. Both fixed and variable-weight DG-TLG circuits operate correctly at a low supply voltage of 1.0 V, and outperform the conventional CMOS equivalents in terms of the most important metrics such as power, speed and area. It is found that variable-weight DG-TLG circuits with analog weight and threshold control have attractive features such as expanded TLG functionality, reduced transistor count, low programming voltages and power-scaling capability, particularly for circuits with four or fewer inputs. (C) 2007 Elsevier Ltd. All rights reserved.
引用
收藏
页码:1301 / 1307
页数:7
相关论文
共 50 条
  • [11] Design of DG-MOSFETs for high linearity performance
    Kaya, S
    Ma, W
    Asenov, A
    2003 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2003, : 68 - 69
  • [12] Reconfigurable Threshold Logic Gates using Memristive Devices
    Thanh Tran
    Rothenbuhler, Adrian
    Smith, Elisa H. Barney
    Saxena, Vishal
    Campbell, Kristy A.
    2012 IEEE SUBTHRESHOLD MICROELECTRONICS CONFERENCE (SUBVT), 2012,
  • [13] Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors
    Kuttappa, Ragh
    Khuon, Lunal
    Nabet, Bahram
    Taskin, Baris
    PROCEEDINGS OF THE 2017 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2017, : 614 - 617
  • [14] The gate misalignment effects of the sub-threshold characteristics of sub-100nm DG-MOSFETs
    Wong, HY
    Shin, KS
    Chan, MS
    2002 IEEE HONG KONG ELECTRON DEVICES MEETING, PROCEEDINGS, 2002, : 91 - 94
  • [15] Some Device Design Considerations to Enhance the Performance of DG-MOSFETs
    Mohapatra, S. K.
    Pradhan, K. P.
    Sahu, P. K.
    TRANSACTIONS ON ELECTRICAL AND ELECTRONIC MATERIALS, 2013, 14 (06) : 291 - 294
  • [16] FPGAs with Reconfigurable Threshold Logic Gates for Improved Performance, Power and Area
    Wagle, Ankit
    Yang, Jinghua
    Dengi, Aykut
    Vrudhula, Sarma
    2018 28TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL), 2018, : 256 - 259
  • [17] Metal Oxide-enabled Reconfigurable Memristive Threshold Logic Gates
    Papandroulidakis, G.
    Khiat, A.
    Serb, A.
    Stathopoulos, S.
    Michalas, L.
    Prodromakis, T.
    2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2018,
  • [18] Reconfigurable Skyrmion Logic Gates
    Luo, Shijiang
    Song, Min
    Li, Xin
    Zhang, Yue
    Hong, Jeongmin
    Yang, Xiaofei
    Zou, Xuecheng
    Xu, Nuo
    You, Long
    NANO LETTERS, 2018, 18 (02) : 1180 - 1184
  • [19] Reconfigurable Plasmonic Logic Gates
    Vladescu, Elena
    Dragoman, Daniela
    PLASMONICS, 2018, 13 (06) : 2189 - 2195
  • [20] Reconfigurable Plasmonic Logic Gates
    Elena Vlădescu
    Daniela Dragoman
    Plasmonics, 2018, 13 : 2189 - 2195