Two modeling techniques for CMOS circuits to enhance test generation and fault simulation for bridging faults

被引：1
|
作者：
Lee, KJ [1 ]
Tang, JJ [1 ]
机构：
[1] NATL CHENG KUNG UNIV,DEPT ELECT ENGN,TAINAN,TAIWAN
来源：
PROCEEDINGS OF THE FIFTH ASIAN TEST SYMPOSIUM (ATS '96) | 1996年
关键词：
D O I：
10.1109/ATS.1996.555154
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：165 / 170
页数：6
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