共 50 条
- [45] A flexible path selection procedure for path delay fault testing 17TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1999, : 152 - 159
- [46] SCINDY: Logic crosstalk delay fault simulation in sequential circuits 18TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: POWER AWARE DESIGN OF VLSI SYSTEMS, 2005, : 820 - 823
- [47] Tackling the Complexity of Exact Path Delay Fault Grading for Path Intensive Circuits 2015 20th IEEE European Test Symposium (ETS), 2015,
- [48] Partial scan delay fault testing of asynchronous circuits 1997 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN - DIGEST OF TECHNICAL PAPERS, 1997, : 728 - 735
- [49] Resynthesis of combinational circuits for path count reduction and for path delay fault testability JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1997, 11 (01): : 43 - 54
- [50] Resynthesis of combinational circuits for path count reduction and for path delay fault testability EUROPEAN DESIGN & TEST CONFERENCE 1996 - ED&TC 96, PROCEEDINGS, 1996, : 486 - 490