Synthesis of robust delay fault testable circuits: Theory

被引：0

作者：

Devadas, S ^{[1
]}

Keutzer, K ^{[1
]}

机构：

[1] SYNOPSYS INC,MT VIEW,CA 94043

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1996年 / 15卷 / 04期

关键词：

D O I：

10.1109/43.494708

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

[No abstract available]

引用

页码：445 / 446

页数：2

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