A probabilistic model for path delay fault testing

Testing path delay faults (PDFs) in VLSI circuits is becoming an important issue as we enter the deep submicron age. However, it is difficult in general since the number of faults is normally very large and most faults are either hard to sensitize or are untestable. In this paper, we propose a probabilistic PDF model. We investigate probability functions for the wire and path delay size to model the fault effect in the circuit under test. In our approach, the delay fault size is assumed to be randomly distributed. An analytical model is proposed to evaluate the PDF coverage. We show that the delay sizes of the unrested paths are actually reduced if these paths are conjoined with other rested good paths. Therefore, using our approach, path selection and synthesis of PDF testable circuits can be done more accurately. Also, given a test set, more accurate fault coverage can be predicted by calculating the mean delay of the paths.