CMOS latchup characterization for LDMOS/LIGBT power integrated circuits

被引：2
|
作者：
Chan, WWT
Sin, JKO
Mok, PKT
Wong, SS
机构：
来源：
ICSE '96 - 1996 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS, PROCEEDINGS | 1996年
关键词：
D O I：
10.1109/SMELEC.1996.616442
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents an unique characterization technique for CMOS latchup in power integrated circuits. To this purpose, test structures are designed and implemented using a 2-mu m twin-well CMOS/LDMOS/LIGBT high voltage process. Lumped element models are used to study the latching mechanism. Cross-talk between LDMOS and CMOS as well as between LIGBT and CMOS are investigated. It is shown that great care should be taken when designing power integrated circuits since CMOS latchup is initiated even at low operating current of the power devices.
引用
收藏
页码：15 / 18
页数：4
相关论文
共 50 条
  • [31] RF LDMOS power amplifier integrated circuits for cellular wireless base station applications
    Shih, Chuming David
    Sjostrom, Johan
    Bagger, Reza
    Andersson, Paul
    Yu, Yinglei
    Ma, Gordon
    Chen, Qiang
    Aberg, Tomas
    2006 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, VOLS 1-5, 2006, : 889 - 892
  • [32] Power and Area Estimation of Discrete Filters in CMOS Integrated Circuits
    Kirei, Botond Sandor
    Farcas, Calin
    Topa, Marina Dana
    2019 SIGNAL PROCESSING ALGORITHMS, ARCHITECTURES, ARRANGEMENTS, AND APPLICATIONS (SPA 2019), 2019, : 67 - 70
  • [33] Robust design of low power CMOS analogue integrated circuits
    Tarim, TB
    Ismail, M
    IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 2001, 148 (04): : 197 - 204
  • [34] CMOS building block for Smart-Power Integrated Circuits
    dosReis, CA
    Santiago, AS
    ICECS 96 - PROCEEDINGS OF THE THIRD IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS, VOLS 1 AND 2, 1996, : 892 - 895
  • [35] Highly Integrated Power Managemant Integrated Circuits in Advanced Cmos Process Technologies
    Manninger, Mario
    ANALOG CIRCUIT DESIGN: HIGH-SPEED CLOCK AND DATA RECOVERY, HIGH-PERFORMANCE AMPLIFIERS, POWER MANAGEMENT, 2009, : 303 - 316
  • [36] EXPERIMENTAL METHODS FOR DETERMINING LATCHUP PATHS IN INTEGRATED-CIRCUITS
    JOHNSTON, AH
    BAZE, MP
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1985, 32 (06) : 4260 - 4265
  • [37] COMPUTER-AIDED LATCHUP ANALYSIS OF INTEGRATED-CIRCUITS
    STULTZ, TJ
    CROWLEY, JL
    HARTOOG, MR
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1981, 28 (06) : 4311 - 4313
  • [38] NEW TRANSIENT CHARACTERIZATION OF LATCHUP PHENOMENON IN CMOS CELL
    ROCHE, FM
    BOCUS, SD
    GIRARD, P
    BARILLE, R
    MICROELECTRONIC ENGINEERING, 1992, 19 (1-4) : 79 - 82
  • [39] An SOI LDMOS/CMOS/BJT technology for integrated power amplifiers used in wireless transceiver applications
    Kumar, M
    Tan, Y
    Sin, JKO
    Cai, J
    IEEE ELECTRON DEVICE LETTERS, 2001, 22 (03) : 136 - 138
  • [40] Terahertz CMOS Integrated Circuits
    Lee, Thomas H.
    2014 IEEE INTERNATIONAL SYMPOSIUM ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY (RFIT): SILICON TECHNOLOGY HEATS UP FOR THZ, 2014,
12345