CMOS latchup characterization for LDMOS/LIGBT power integrated circuits

被引：2
|
作者：
Chan, WWT
Sin, JKO
Mok, PKT
Wong, SS
机构：
来源：
ICSE '96 - 1996 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS, PROCEEDINGS | 1996年
关键词：
D O I：
10.1109/SMELEC.1996.616442
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents an unique characterization technique for CMOS latchup in power integrated circuits. To this purpose, test structures are designed and implemented using a 2-mu m twin-well CMOS/LDMOS/LIGBT high voltage process. Lumped element models are used to study the latching mechanism. Cross-talk between LDMOS and CMOS as well as between LIGBT and CMOS are investigated. It is shown that great care should be taken when designing power integrated circuits since CMOS latchup is initiated even at low operating current of the power devices.
引用
收藏
页码：15 / 18
页数：4
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