A 12 Bit 500MS/s SHA-less ADC in 0.18um CMOS

被引：0

作者：

Li, Liang ^{[1
]}

Xu, Mingyuan ^{[1
]}

Huang, Xingfa ^{[1
]}

Shen, Xiaofeng ^{[1
]}

Fu, Dongbing ^{[2
]}

Chen, Xi ^{[2
]}

Pujie ^{[2
]}

机构：

[1] Sci & Technol Analog Integrated Circuit Lab, Chongqing 400060, Peoples R China

[2] Sichuan Inst Solide State Circuits, Chongqing 400060, Peoples R China

来源：

7TH IEEE INTERNATIONAL NANOELECTRONICS CONFERENCE (INEC) 2016 | 2016年

关键词：

switched capacitor; SHA-less; input buffer; CMOS; SFDR;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a 12 bit 500MS/s SHA-less ADC is described. The ADC has an integrated input buffer with a new linearization technique that improves its distortion. Eight pipeline stages with fully differential switched capacitor architecture follow the input buffer. Each of stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier(MDAC). A 0.18 mu m CMOS process with 3.3V/1.8V analog power supply is used in the design. This ADC achieves an SNR of 65dB and an SFDR of 82dB for sampling analog input frequencies up to 250MHz.

引用

页数：2

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