A low power 0.18um 10Gb/s CMOS 16:1 multiplexer

被引：0
|
作者：
Zhou H. [1 ]
Feng J. [1 ]
机构：
[1] Institute of RF- and OE-ICs, Southeast University
来源：
Gaojishu Tongxin/Chinese High Technology Letters | 2010年 / 20卷 / 04期
关键词：
CMOS; Low power; Multiplexer; Optical communication; Ultra-high speed;
D O I：
10.3772/j.isan.1002-0470.2010.04.014
中图分类号：
学科分类号：
摘要：
A 10Gb/s 16:1 multiplexer was fabricated using the semiconductor manufacturing international corporation (SMIC) 0.18μm complementary metal oxide semiconductor (CMOS) process. The total power consumption of the chip is 160mW. The tree-type structure is adopted. The low speed (622Mb/s → 5Gb/s) multiplexer cell and the low speed (2.5GHz→ 622MHz) frequency divider cell were implemented using the COMS logic, while the high speed (5Gb/s → 10Gb/s) multiplexer cell and the high speed (5GHz→ 2.5GHz) frequency divider cell were implemented using the source coupled field effect transistor logic (SCFL). The test results of the 16:1 multiplexer show that its output data rate is up to 10Gb/s at a supply voltage of 1.8V, and the peak-to-peak value of output single signal is 180mV.
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页码：410 / 414
页数：4
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