FPGA Implementation of High Speed Multiplier with Optimized Reduction Phase

被引：1

作者：

Singh, Arpita ^{[1
]}

Sharma, Abhay ^{[2
]}

Kumari, Priyanka ^{[1
]}

机构：

[1] Graph Era Univ, Dept Elect & Commun Engn, Dehra Dun 248002, Uttarakhand, India

[2] Graph Era Hill Univ, Dept Elect & Commun Engn, Dehra Dun 248002, Uttarakhand, India

来源：

INTELLIGENT COMMUNICATION, CONTROL AND DEVICES, ICICCD 2017 | 2018年 / 624卷

关键词：

Wallace tree multiplier; Reduced partial products; Carry look-ahead adder; Delay; LUTs;

D O I：

10.1007/978-981-10-5903-2_21

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Multipliers play an important role in DSP applications hence, the delay executed by them is a dominating factor. Various multiplication algorithms are used to enhance the speed of the device. All these multipliers are then compared based on look up table (LUTs) and path delays. The simulated results show that the Wallace tree multiplier is the fastest multiplier, and by using carry look-ahead adder (CLA) for addition, delay is further reduced.

引用

页码：187 / 195

页数：9

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