Implementation of a High Speed Time Resolved Error Detector Utilising a High Speed FPGA

被引：0

作者：

O'Dowd, John A. ^{[1
]}

Bessler, Vivian M. ^{[1
]}

Ibrahim, Selwan K. ^{[1
]}

Walsh, Anthony J. ^{[1
]}

Peters, F. H. ^{[1
]}

Corbett, B. ^{[1
]}

Roycroft, B. ^{[1
]}

Brien, P. O. ^{[1
]}

Ellis, Andrew D. ^{[1
]}

机构：

[1] Natl Univ Ireland Univ Coll Cork, Tyndall Natl Inst, Cork, Ireland

来源：

2011 13TH INTERNATIONAL CONFERENCE ON TRANSPARENT OPTICAL NETWORKS (ICTON) | 2011年

关键词：

Time-resolved error detector; Packet switching; Tuneable lasers; Wavelength switching;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We demonstrate a time-resolved bit error rate detector utilising a field programmable gate array. The proposed detector offers 93 ps resolution operating at 10.7 Gb/s and allows for all the data received to contribute to the measurement allowing low bit error rates to be measured at high speed. Via synchronisation of both the detector and a high speed scope, the bit error rate and the corresponding individual eyes are identified. The operation of the detector is demonstrated by characterising a fast switching tuneable laser.

引用

页数：4

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