FPGA implementation of AES algorithm for high speed applications

被引:0
|
作者
S. Sridevi Sathya Priya
P. Karthigaikumar
Narayana Ravi Teja
机构
[1] Karunya Institute of Technology and Sciences,
[2] Karpagam College of Engineering,undefined
关键词
AES; Encryption; S-Box; Mix Column; Pipelining;
D O I
暂无
中图分类号
学科分类号
摘要
The main objective of this paper is to design and implement High throughput, area efficient AES encryption algorithm on FPGA for security purposes. The high speed and area efficiency is achieved by designing an area efficient and high throughput structural S-Box architecture for AES encryption process. A combinational logic circuit based Rijndael Low area high speed S-Box is designed. The results compared with conventional S-Box. The speed and propagation delay of the S-Box are calculated for the designed S-Box. The proposed S-Box is used in AES encryption process. To further increase the speed of the encryption process efficient structure of Mix column is also proposed. This Mix column structure is used to achieve high throughput. The proposed S-Box and Mix Column are used in AES encryption. This proposed AES structure is implemented in FPGA Virtex 5.The results are compared with the conventional implementation.
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页码:115 / 125
页数:10
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