FPGA implementation of AES algorithm for high speed applications

被引：0
|
作者：
S. Sridevi Sathya Priya
P. Karthigaikumar
Narayana Ravi Teja
机构：
[1] Karunya Institute of Technology and Sciences,
[2] Karpagam College of Engineering,undefined
来源：
Analog Integrated Circuits and Signal Processing | 2022年 / 112卷
关键词：
AES; Encryption; S-Box; Mix Column; Pipelining;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
The main objective of this paper is to design and implement High throughput, area efficient AES encryption algorithm on FPGA for security purposes. The high speed and area efficiency is achieved by designing an area efficient and high throughput structural S-Box architecture for AES encryption process. A combinational logic circuit based Rijndael Low area high speed S-Box is designed. The results compared with conventional S-Box. The speed and propagation delay of the S-Box are calculated for the designed S-Box. The proposed S-Box is used in AES encryption process. To further increase the speed of the encryption process efficient structure of Mix column is also proposed. This Mix column structure is used to achieve high throughput. The proposed S-Box and Mix Column are used in AES encryption. This proposed AES structure is implemented in FPGA Virtex 5.The results are compared with the conventional implementation.
引用
收藏
页码：115 / 125
页数：10
相关论文
共 50 条
  • [1] FPGA implementation of AES algorithm for high speed applications
    Priya, S. Sridevi Sathya
    Karthigaikumar, P.
    Teja, Narayana Ravi
    [J]. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2022, 112 (01) : 115 - 125
  • [2] FPGA Implementation of High speed VLSI Architectures for AES Algorithm
    Kshirsagar, R. V.
    Vyawahare, M. V.
    [J]. PROCEEDINGS OF THE 2012 FIFTH INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN ENGINEERING AND TECHNOLOGY (ICETET 2012), 2012, : 239 - 242
  • [3] A High-Speed FPGA Implementation of AES for Large Scale Embedded Systems and its Applications
    Harb, Salah
    Ahmad, M. Omair
    Swamy, M. N. S.
    [J]. 2022 13TH INTERNATIONAL CONFERENCE ON INFORMATION AND COMMUNICATION SYSTEMS (ICICS), 2022, : 59 - 64
  • [4] A high speed FPGA implementation of the Rijndael algorithm
    Sever, R
    Ismailoglu, AN
    Tekmen, YC
    Askar, M
    Okcan, B
    [J]. PROCEEDINGS OF THE EUROMICRO SYSTEMS ON DIGITAL SYSTEM DESIGN, 2004, : 358 - 362
  • [5] Implementation of Pipelined Sobel Edge Detection Algorithm on FPGA for High Speed Applications
    Vanishree
    Reddy, K. V. Ramana
    [J]. 2013 INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN COMMUNICATION, CONTROL, SIGNAL PROCESSING AND COMPUTING APPLICATIONS (IEEE-C2SPCA-2013), 2013,
  • [6] AES Algorithm Optimization and FPGA Implementation
    Liu, Yufeng
    Xu, Xiangyang
    Su, Hao
    [J]. 2019 3RD INTERNATIONAL WORKSHOP ON RENEWABLE ENERGY AND DEVELOPMENT (IWRED 2019), 2019, 267
  • [7] EFFICIENT IMPLEMENTATION OF AES ALGORITHM ON FPGA
    Deshpande, Hrushikesh S.
    Karande, Kailash J.
    Mulani, Altaaf O.
    [J]. 2014 INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND SIGNAL PROCESSING (ICCSP), 2014,
  • [8] An efficient high speed AES implementation using Traditional FPGA and LabVIEW FPGA platforms
    Rao, Muzaffar
    Kaknjo, Admir
    Omerdic, Edin
    Toal, Daniel
    Newe, Thomas
    [J]. 2018 INTERNATIONAL CONFERENCE ON CYBER-ENABLED DISTRIBUTED COMPUTING AND KNOWLEDGE DISCOVERY (CYBERC 2018), 2018, : 93 - 100
  • [9] High-Speed FPGA Implementation of Secure Hash Algorithm for IPSec and VPN Applications
    Athanasios P. Kakarountas
    Haralambos Michail
    Athanasios Milidonis
    Costas E. Goutis
    George Theodoridis
    [J]. The Journal of Supercomputing, 2006, 37 : 179 - 195
  • [10] High-speed FPGA implementation of secure hash algorithm for IPSec and VPN applications
    Kakarountas, Athanasios P.
    Michail, Haralambos
    Milidonis, Athanasios
    Goutis, Costas E.
    Theodoridis, George
    [J]. JOURNAL OF SUPERCOMPUTING, 2006, 37 (02): : 179 - 195
12345