Improving Performance and Fabrication Metrics of Three-Dimensional ICs by Multiplexing Through-Silicon Vias

Three-dimensional (3D) integration using through-silicon vias (TSVs) offers advantages over traditional 2D integration, however there are still several challenges originated from stacking dies. The main challenges in 3D-ICs are the large area overhead of the TSVs, low yield due to stacking several dies, and the increased cost of fabrication. In this paper a TSV multiplexing technique using so called TSV-BOX is proposed, which substitutes two TSVs with one TSV plus some extra hardware, but totally resulting in smaller die area. However, it does not impact the performance of the circuit. The TSV-BOX increases the total yield and reduces power consumption and fabrication cost due to the reduced TSV count. For a 100 mm(2) die with 2x10(5) TSV count and TSV diameter of 8 mu m, the TSV-BOX could achieve 10% reduction in area, a 78% reduction in cost, and finally the yield could be enhanced by 24 times the original yield.