Thermal Analysis of Three-Dimensional ICs, Investigating The Effect of Through-Silicon Vias and Fabrication Parameters

Three-dimensional (3D) integration technology is a promising technology for future due to multiple advantages over traditional 2D integrated circuits. However, dividing an original large die into smaller ones and stacking them decreases thermal conductivity of the chip and therefore an increase in temperature is expected. Through-silicon vias (TSVs) which implement vertical interconnections for the stacked dies in 3D chips can help transferring heat to the heat sink of the chip. Some recent works introduce techniques for reducing the TSV count which may cause worsening heat conduction, hence increase the peak temperature of the chip. In this paper the effect of the TSV count as well as four other fabrication parameters on the maximum 3D chip temperature is investigated. It is observed that reducing TSV count has a negative side effect on maximum temperature in all studied cases and increasing number of layers of the 3D stack has the most significant negative effect on maximum temperature. For example, increasing number of layers from two to four increases maximum temperature by 37.5% at a constant TSV pitch of 80 mu m. While increasing TSV count four times by doubling TSV pitch from 40 mu m to 80 mu m increases maximum temperature by about 10% for six layers 3D stack.