Electrothermal modelling and characterisation of submicron through-silicon carbon nanotube bundle vias for three-dimensional ICs

被引:15
|
作者
Zhao, Wen-Sheng [1 ]
Sun, Lingling [1 ]
Yin, Wen-Yan [2 ]
Guo, Yong-Xin [3 ]
机构
[1] Hangzhou Dianzi Univ, Microelect CAD Ctr, Minist Educ, Key Lab RF Circuits & Syst, Hangzhou 310018, Zhejiang, Peoples R China
[2] Zhejiang Univ, State Key Lab, MOI, Ctr Opt & EM Res, Hangzhou 310058, Zhejiang, Peoples R China
[3] Natl Univ Singapore, Dept Elect & Comp Engn, Singapore 117576, Singapore
来源
MICRO & NANO LETTERS | 2014年 / 9卷 / 02期
关键词
carbon nanotubes; equivalent circuits; reliability; three-dimensional integrated circuits; electrothermal modelling; through-silicon carbon nanotube bundle via; 3D IC; TS-CNTBV; equivalent circuit model; TSV dimension; PERFORMANCE ANALYSIS; 3-D ICS; INTERCONNECTS; GROWTH; DESIGN;
D O I
10.1049/mnl.2013.0553
中图分类号
TB3 [工程材料学];
学科分类号
0805 ; 080502 ;
摘要
A submicron through-silicon carbon nanotube bundle via (TS-CNTBV) is characterised based on its equivalent circuit model. As the through-silicon vias (TSV) dimensions are scaled down to the nanoscale, it is proved that the single-walled carbon nanotube bundle can provide a better performance and reliability than the conventional metals, whereas the multiwalled carbon nanotube becomes unsuitable for the TSV applications. Both the metal-oxide-semiconductor and the temperature effects are considered and treated appropriately in the modelling of the TS-CNTBV. The process requirement and the energy delay product of the through-silicon-single-walled carbon nanotube bundle via are investigated, and the equivalent thermal conductivity of the silicon substrate with the TS-CNTBVs is obtained and analysed finally.
引用
收藏
页码:123 / 126
页数:4
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