Impact of Doping Density on Junctionless Gate Stack FD-SOI MOSFET for Analog/RF Application

被引：2

作者：

Singh, Jyotsana ^{[1
]}

Yadava, Narendra ^{[1
]}

Chauhan, R. K. ^{[1
]}

机构：

[1] Madan Mohan Malaviya Univ Technol, Dept Elect & Commun Engn, Gorakhpur 273010, Uttar Pradesh, India

来源：

2019 IEEE 5TH INTERNATIONAL CONFERENCE FOR CONVERGENCE IN TECHNOLOGY (I2CT) | 2019年

关键词：

High-k; Analog and RF FOMs DDL-GSJL; HDSD-GSJL; FD-SOI; MOSFET;

D O I：

10.1109/i2ct45611.2019.9033758

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

This paper examine the impact of Double Doped Layer Gate Stack Junctionless (DDL-GSJL) MOSFET and Highly Doped Source Drain Gate Stack Junctionless (HDSD-GSJL) MOSFET. We compare the performance of proposed MOSFET, with uniformly doped conventional junctionless MOSFET. The proposed MOSFET has no pn junction, only n-type non-uniform doping is used. Non-uniform doping is distributed in a horizontal and vertical manner. A high-k material (Si3N4) is used as gate stack to control the leakage current and increase the I-ON/IOFF. This paper present analog and RF figure of merits (FOM). In the paper major FOMs, output conductance (g(d)), transconductance (g(m)), cut-off frequency (f(T)), transconductance frequency product (TFP) is analyzed. The simulated results reflect that HDSD-GSJL MOSFET exhibit high transconductance, high cut-off frequency and high transconductance frequency product. The structure is designed and analyzed using ATLAS 2D TCAD tools.

引用

页数：4

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