On Modeling Faults in FinFET Logic Circuits

FinFET transistor has much better short-channel characteristics than traditional planar CMOS transistor and will be widely used in next generation technology. Due to its significant structural difference from conventional planar devices, it is essential to revisit whether existing fault models are applicable to detect faults in FinFET logic gates. In this paper, we study some unique defects in FinFET logic circuits and simulate their faulty behavior. Our simulation study shows that most of the defects can be covered with existing fault models, but they vary under different cases and test strategies may need to be augmented to target them.