Integrating flipped drain and power gating techniques for efficient FinFET logic circuits

Power dissipation is a main attention for designing complementary metal oxide semiconductor Very Large Scale Integration (VLSI) circuits in deep sub-micron technology. Constant field device scaling leads to high transistor density, reduction in power supply, lower threshold voltage, and reduction in oxide thickness. This gives rise to short channel effects and increases the leakage currents causing power dissipation. In this paper, based on literature survey, new flipped drain gating (FDG) technique is proposed for mitigation of leakage currents; further FDG technique is integrated with power gating technique which makes power dissipation lower than FDG. Proposed techniques are integrated with FinFET technology and applied on Logic Gates and bench mark circuits on HSPICE simulator. Simulation is carried out at 27 degrees C temperature by using 20 to 7-nm Berkley Predictive Technology Module. Simulation results at 10-MHz frequency shows maximum saving in leakage power using FDG technique at input vector 01 as 80.35% compared with conventional drain gating for EXOR logic. Similarly, FDG technique saves maximum dynamic power of 25.98% when compared with conventional drain gating for AND logic.