ESD protection structure enhancement against Latch-Up issue using TCAD Simulation

被引：0
|
作者：
Bourgeat, Johan [1 ]
Guitard, Nicolas [1 ]
David, Florence [1 ]
机构：
[1] STMicroelectronics, 850 Rue Jean Monnet, F-38920 Crolles, France
来源：
2017 39TH ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM (EOS/ESD) | 2017年
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D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
During IO qualification's LUP tests in CMOS28nm Bulk technology, undesired ESD structure triggering has been found to be the root cause of LUP fails. Deeper test analysis identifies the combination of IOs abutment sequence that generate the fail. The understanding of the phenomenon is investigated through a specific TCAD simulation set-up.
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页数：9
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