ESD protection structure enhancement against Latch-Up issue using TCAD Simulation

被引：0
|
作者：
Bourgeat, Johan [1 ]
Guitard, Nicolas [1 ]
David, Florence [1 ]
机构：
[1] STMicroelectronics, 850 Rue Jean Monnet, F-38920 Crolles, France
来源：
2017 39TH ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM (EOS/ESD) | 2017年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
During IO qualification's LUP tests in CMOS28nm Bulk technology, undesired ESD structure triggering has been found to be the root cause of LUP fails. Deeper test analysis identifies the combination of IOs abutment sequence that generate the fail. The understanding of the phenomenon is investigated through a specific TCAD simulation set-up.
引用
收藏
页数：9
相关论文
共 50 条
  • [1] Using an SCR as ESD protection without latch-up danger
    Notermans, G
    Kuper, F
    Luchies, JM
    MICROELECTRONICS AND RELIABILITY, 1997, 37 (10-11): : 1457 - 1460
  • [2] Latch-up Free ESD Protection Design With SCR Structure in Advanced CMOS Technology
    Wang, Chang-Tzu
    Tang, Tien-Hao
    Su, Kuan-Cheng
    2011 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2011,
  • [3] Analysis of external latch-up protection test structure design using numerical simulation
    Palser, K
    Concannon, A
    Duffy, R
    Mathewson, A
    MICROELECTRONICS RELIABILITY, 1999, 39 (05) : 647 - 659
  • [4] Emitter injection control in LVTSCR for latch-up free ESD protection
    Vashchenko, V
    Concannon, A
    Ter Beek, M
    Hopper, P
    2002 23RD INTERNATIONAL CONFERENCE ON MICROELECTRONICS, VOLS 1 AND 2, PROCEEDINGS, 2002, : 741 - 744
  • [5] ESD protection Diode with Guard Ring Layout Optimized for Latch-up Immunity Enhancement in FinFET technology
    Huang, Kai-Ping
    Peng, Po-Lin
    Chu, Li-Wei
    Chang, Yi-Feng
    Chang, Tzu-Heng
    Lee, Jam-Wem
    Chen, Kuo-Ji
    Song, Ming-Hsiang
    2019 41ST ANNUAL EOS/ESD SYMPOSIUM (EOS/ESD), 2019,
  • [6] A Non-Typical Latch-up Event on BV ESD Protection
    Wang, Shih-Yu
    Huang, Hao-Chan
    He, Chieh-Wei
    Chang, Yao-Wen
    Lu, Tao-Cheng
    Chen, Kuang-Chao
    Lu, Chih-Yuan
    2014 36TH ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM (EOS/ESD), 2014,
  • [7] Design of ESD Protection with SCR-based Structures for Latch-up Immunity
    Jung, Jin Woo
    Lee, Byung Seok
    Choi, Yong Nam
    Han, Jung Woo
    Koo, Yong Seo
    2013 IEEE INTERNATIONAL CONFERENCE OF IEEE REGION 10 (TENCON), 2013,
  • [8] LVTSCR structures for latch-up free ESD protection of BiCMOS RF circuits
    Vashchenko, V
    Concannon, A
    ter Beek, M
    Hopper, P
    MICROELECTRONICS RELIABILITY, 2003, 43 (01) : 61 - 69
  • [9] Solving ESD protection latch-up guard ring issues during electrostatic discharge (ESD) events
    Trémouilles, D
    Bafleur, M
    Bertrand, G
    Nolhier, N
    Mauran, N
    Lescouzeres, L
    PROCEEDINGS OF THE 2003 BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING, 2003, : 133 - 136
  • [10] ESD and latch-up reliability for nanometer CMOS technologies
    Duvvury, C
    Boselli, G
    IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, : 933 - 936
12345