Design of Low Power, High Speed PLL Frequency Synthesizer using Dynamic CMOS VLSI Technology

被引：0

作者：

Nirmalraj, T. ^{[1
]}

Radhakrishnan, S. ^{[1
]}

Karn, Rakesh Kumar ^{[2
]}

Pandiyan, S. K. ^{[2
]}

机构：

[1] SASTRA Univ, Srinivasa Ramunujan Ctr, Dept Elect & Commun Engn, Thanjavur, Tamil Nadu, India

[2] SASTRA Univ, Dept Elect & Commun Engn, Thanjavur, Tamil Nadu, India

来源：

2017 IEEE INTERNATIONAL CONFERENCE ON POWER, CONTROL, SIGNALS AND INSTRUMENTATION ENGINEERING (ICPCSI) | 2017年

关键词：

component; CMOS Dynamic logic; PLL; VCO; DSCH2; Microwind; 2.6;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In microprocessor design, it is very challenge to handle the power consumption. Power is an important parameter in various communication systems. Phase locked loop (PLL) is a versatile method which is used in frequency synthesis methods. A dynamic logic based CMOS is proposed to design phase detector, VCO and loop filter. The CMOS dynamic logic is the fastest logic in all the CMOS logic families. The DSCH2 CAD tool is used in the design of logical circuits and Microwind 2.6 tool using 120nm CMOS technology is used to measure the parametric analysis. The speed of transition time between the synthesized frequencies gives the bandwidth of loop filter. In the dynamic CMOS logic PIA, the power is reduced to 0.13mW and speed is improved to 0.50GHz.

引用

页码：1074 / 1076

页数：3

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