A high-speed hardware implementation of the Hermes8-128 stream cipher

被引：1

作者：

Kitsos, Paris ^{[1
]}

Kaiser, Ulrich ^{[2
]}

机构：

[1] Hellen Open Univ, Sch Sci & Technol, Comp Sci, Patras, Greece

[2] Texas Instruments Deutschland GmbH, D-85350 Freising Weihenstephan, Germany

来源：

2007 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1-3 | 2007年

关键词：

D O I：

10.1109/ECCTD.2007.4529608

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An efficient high-speed hardware implementation of the Hermes8-128 stream cipher is presented in this paper. Hermes8-128 is proposed for hardware based implementations in the eSTREAM project [1]. Two FPGA devices are used for the hardware implementations. Especially, the XILLNX (Spartan-2) 2S100-6 and (VIRTEX-4) 4VFX12-11 are used. A maximum throughput of 56.5 Mbps can be achieved with a clock frequency of 49 MHz with a XC2S100-6 device, while a throughput of 361 Mbps at 313 MHz is achieved with the 4VFX12-11 device. Since now only one previous reported Hermes8-128 hardware implementation exists, a comparison with the proposed one is given.

引用

页码：364 / +

页数：2

共 50 条

[1] High-speed implementation of ubiquitous stream cipher
Lee, H
Kim, H
[J]. System Simulation and Scientific Computing, Vols 1 and 2, Proceedings, 2005, : 1624 - 1631
[2] High-speed stream cipher
Ooi, HS
[J]. 18TH INTERNATIONAL CONFERENCE ON ADVANCED INFORMATION NETWORKING AND APPLICATIONS, VOL 2 (REGULAR PAPERS), PROCEEDINGS, 2004, : 39 - 42
[3] Hardware Implementation and Performance Analysis of NLM-128 Stream Cipher
Lee, Soh Yee
Lee, HoonJae
[J]. CONVERGENCE AND HYBRID INFORMATION TECHNOLOGY, 2011, 206 : 446 - 453
[4] CASTREAM: A High-speed, Secure Stream Cipher Suitable for Both Hardware and Software
Das, Sourav
Roychowdhury, Dipanwita
[J]. JOURNAL OF CELLULAR AUTOMATA, 2014, 9 (2-3) : 153 - 166
[5] High-speed hardware implementations of the KASUMI block cipher
Kitsos, P
Galanis, MD
Koufopavlou, O
[J]. 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS, 2004, : 549 - 552
[6] Parallel stream cipher for secure high-speed communications
Lee, H
Moon, S
[J]. SIGNAL PROCESSING, 2002, 82 (02) : 259 - 265
[7] An Improved Hardware Implementation of the Grain Stream Cipher
Mansouri, Shohreh Sharif
Dubrova, Elena
[J]. 13TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS, 2010, : 433 - 440
[8] Design and implementation of a high-speed reconfigurable cipher chip
Gao Nana
[J]. Journal of Systems Engineering and Electronics, 2006, (04) : 712 - 716
[9] Designing High-Throughput Hardware Accelerator for Stream Cipher HC-128
Chattopadhyay, Anupam
Khalid, Ayesha
Maitra, Subhamoy
Raizada, Shashwat
[J]. 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), 2012, : 1448 - 1451
[10] ARQ PROTOCOLS FOR HIGH-SPEED HARDWARE IMPLEMENTATION
GOPAL, I
ROM, R
[J]. COMPUTER NETWORKS AND ISDN SYSTEMS, 1995, 27 (05): : 677 - 689

← 1 2 3 4 5 →