A high-speed hardware implementation of the Hermes8-128 stream cipher

被引：1

作者：

Kitsos, Paris ^{[1
]}

Kaiser, Ulrich ^{[2
]}

机构：

[1] Hellen Open Univ, Sch Sci & Technol, Comp Sci, Patras, Greece

[2] Texas Instruments Deutschland GmbH, D-85350 Freising Weihenstephan, Germany

来源：

2007 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1-3 | 2007年

关键词：

D O I：

10.1109/ECCTD.2007.4529608

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An efficient high-speed hardware implementation of the Hermes8-128 stream cipher is presented in this paper. Hermes8-128 is proposed for hardware based implementations in the eSTREAM project [1]. Two FPGA devices are used for the hardware implementations. Especially, the XILLNX (Spartan-2) 2S100-6 and (VIRTEX-4) 4VFX12-11 are used. A maximum throughput of 56.5 Mbps can be achieved with a clock frequency of 49 MHz with a XC2S100-6 device, while a throughput of 361 Mbps at 313 MHz is achieved with the 4VFX12-11 device. Since now only one previous reported Hermes8-128 hardware implementation exists, a comparison with the proposed one is given.

引用

页码：364 / +

页数：2

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