ARQ PROTOCOLS FOR HIGH-SPEED HARDWARE IMPLEMENTATION

In order to fully exploit high speed communication channels the processing burden at the end points must be reduced. One way in which this can be done is by shifting the implementation of protocols from software to specialized, dedicated hardware. This process is made easier if the protocols are designed with hardware implementation in mind. In this paper we consider a family of ARQ protocols that can be implemented through relatively simple hardware-one or more FIFO buffers and some limited state information. With a single FIFO buffer the protocol is identical to a regular Go-Back-N. By increasing the number of FIFO buffers we can reach a full selective repeat. The main result is to show that, for typical error rates, performance close to selective repeat can be obtained with two or three FIFO buffers. The family of protocols is described in detail followed by throughput analysis. For the two buffer case a closed-form solution is obtained while for other cases simulation results are given.