Novel SET Mitigation Technique for Clock Distribution Networks

With the fabrication technology progressively scaling down, the clock distribution network (CDN) in the integrated circuit is increasingly vulnerable to the single event transient (SET). In the worst case, the SET on the CDN can lead to failure of the whole circuit. In this paper, a novel SET mitigation technique for the CDN is proposed, in which the clock inverter is redesigned with dual inputs and dual outputs. Based on this kind of dual-in-and-dual-out inverter, the hardened CDN of a case circuit was designed and evaluated. Both the post-layout simulations and heavy ion radiation experiments show that, compared with the unhardened CDN, the probability capturing SET at the leaf nodes of the hardened CDN is significantly reduced. The area, performance, and power overheads introduced by this mitigation technique are negligible. Moreover, the SET mitigation technique is easy to realize and can be used in the CDNs with different topologies.