Novel SET Mitigation Technique for Clock Distribution Networks

被引:9
|
作者
Hao, Peipei [1 ]
Chen, Shuming [1 ]
Huang, Pengcheng [1 ]
Chen, Jianjun [1 ]
Liang, Bin [1 ]
机构
[1] Natl Univ Def Technol, Coll Comp, Changsha 410073, Hunan, Peoples R China
基金
中国国家自然科学基金;
关键词
Single event transient (SET); clock distribution network (CDN); SET sensitivity; SET propagation; SET mitigation; charge sharing effect; SINGLE EVENT UPSETS; 130; NM; CHARGE; CIRCUITS; LOGIC; TECHNOLOGY; WELL;
D O I
10.1109/TDMR.2018.2802442
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
With the fabrication technology progressively scaling down, the clock distribution network (CDN) in the integrated circuit is increasingly vulnerable to the single event transient (SET). In the worst case, the SET on the CDN can lead to failure of the whole circuit. In this paper, a novel SET mitigation technique for the CDN is proposed, in which the clock inverter is redesigned with dual inputs and dual outputs. Based on this kind of dual-in-and-dual-out inverter, the hardened CDN of a case circuit was designed and evaluated. Both the post-layout simulations and heavy ion radiation experiments show that, compared with the unhardened CDN, the probability capturing SET at the leaf nodes of the hardened CDN is significantly reduced. The area, performance, and power overheads introduced by this mitigation technique are negligible. Moreover, the SET mitigation technique is easy to realize and can be used in the CDNs with different topologies.
引用
收藏
页码:105 / 113
页数:9
相关论文
共 50 条
  • [31] An ECO technique for removing crosstalk violations in clock networks
    Kumar, Amit
    Chakrabarty, Krishnendu
    Mohan, Chunduri Rama
    20TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: TECHNOLOGY CHALLENGES IN THE NANOELECTRONICS ERA, 2007, : 283 - +
  • [32] A clock distribution technique with an automatic skew compensation circuit
    Sutoh, H
    Yamakoshi, K
    IEICE TRANSACTIONS ON ELECTRONICS, 1998, E81C (02) : 277 - 283
  • [33] Detection and Mitigation of Extreme Losses in Distribution Networks
    Paulos, Jose Pedro
    Fidalgo, Jose Nuno
    Saraiva, J. T.
    Barbosa, Nuno
    2021 IEEE MADRID POWERTECH, 2021,
  • [34] PEVs Modeling and Impacts Mitigation in Distribution Networks
    Shaaban, Mostafa F.
    Atwa, Yasser M.
    El-Saadany, Ehab F.
    IEEE TRANSACTIONS ON POWER SYSTEMS, 2013, 28 (02) : 1122 - 1131
  • [35] A Novel Variation Insensitive Clock Distribution Methodology
    Hussein, Ezz El-Din O.
    Ismail, Yehea I.
    2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 1743 - 1746
  • [36] Power dissipation in basic global clock distribution networks
    Sobczyk, Artur L.
    Luczyk, Arkadiusz W.
    Pleskacz, Witold A.
    PROCEEDINGS OF THE 2007 IEEE WORKSHOP ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, 2007, : 231 - +
  • [37] HCDN: Hybrid-Mode Clock Distribution Networks
    Islam, Riadul
    Guthaus, Matthew R.
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2019, 66 (01) : 251 - 262
  • [38] Design of clock distribution networks in presence of process variations
    Nekili, M
    Savaria, Y
    Bois, G
    PROCEEDINGS OF THE 8TH GREAT LAKES SYMPOSIUM ON VLSI, 1998, : 95 - 102
  • [39] Electrical and optical clock distribution networks for gigascale microprocessors
    Mule', AV
    Glytsis, EN
    Gaylord, TK
    Meindl, JD
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2002, 10 (05) : 582 - 594
  • [40] Clock distribution networks with on-chip transmission lines
    Mizuno, M
    Anjo, K
    Sumi, Y
    Fukaishi, M
    Wakabayashi, H
    Mogami, T
    Horiuchi, T
    Yamashina, M
    PROCEEDINGS OF THE IEEE 2000 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2000, : 3 - 5