Clock distribution networks with on-chip transmission lines

被引：4

作者：

Mizuno, M ^{[1
]}

Anjo, K ^{[1
]}

Sumi, Y ^{[1
]}

Fukaishi, M ^{[1
]}

Wakabayashi, H ^{[1
]}

Mogami, T ^{[1
]}

Horiuchi, T ^{[1
]}

Yamashina, M ^{[1
]}

机构：

[1] NEC Corp Ltd, Kanagawa, Japan

来源：

PROCEEDINGS OF THE IEEE 2000 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2000年

关键词：

D O I：

10.1109/IITC.2000.854080

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Today's fabrication process scaling enables on-chip lossy transmission lines to be used for long interconnects and high-speed clocking. Advantages and design tradeoffs of on-chip transmission lines are discussed and a 100-mm(2) 5-GHz clocking chip using on-chip transmission lines is introduced.

引用

页码：3 / 5

页数：3

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