High Performance CMOS FDSOI Devices activated at Low Temperature

被引：0

作者：

Pasini, L. ^{[1
,2
,3
]}

Batude, P. ^{[1
]}

Lacord, J. ^{[1
]}

Casse, M. ^{[1
]}

Mathieu, B. ^{[1
]}

Sklenard, B. ^{[1
]}

Luce, E. Piegas ^{[1
]}

Micout, J. ^{[1
,3
]}

Payet, A. ^{[1
]}

Mazen, F. ^{[1
]}

Besson, P. ^{[1
]}

Ghegin, E. ^{[1
,2
]}

Borrel, J. ^{[1
,2
]}

Daubriac, R. ^{[4
]}

Hutin, L. ^{[1
]}

Blachier, D. ^{[1
]}

Barge, D. ^{[2
]}

Chhun, S. ^{[2
]}

Mazzocchi, V. ^{[1
]}

Cros, A. ^{[2
]}

Barnes, J-P. ^{[1
]}

Saghi, Z. ^{[1
]}

Delaye, V. ^{[1
]}

Rambal, N. ^{[1
]}

Lapras, V. ^{[1
]}

Mazurier, J. ^{[1
]}

Weber, O. ^{[1
]}

Andrieu, F. ^{[1
]}

Brunet, L. ^{[1
]}

Fenouillet-Beranger, C. ^{[1
]}

Rafhay, Q. ^{[3
]}

Ghibaudo, G. ^{[3
]}

Cristiano, F. ^{[4
]}

Haond, M. ^{[2
]}

Boeuf, F. ^{[2
]}

Vinet, M. ^{[1
]}

机构：

[1] Minatec Grenoble, Leti, CEA, Grenoble, France

[2] STMicroelect Crolles, Crolles, France

[3] Minatec Grenoble INP, IMEP, LAHC, Grenoble, France

[4] CNRS, LAAS, Toulouse, France

来源：

2016 IEEE SYMPOSIUM ON VLSI TECHNOLOGY | 2016年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

3D sequential integration requires top FETs processed with a low thermal budget (500-600 degrees C). In this work, high performance low temperature FDSOI devices are obtained thanks to the adapted extension first architecture and the introduction of mobility boosters (pMOS: SiGe 27% channel / SiGe:B 35% RSD and nMOS: SiC:P RSD). This first demonstration of n and p extension first FDSOI devices shows that low temperature activated device can match the performance of a device with state-of-the-art high temperature process (above 1000 degrees C).

引用

页数：2

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