A Disturb Free Read Port 8T SRAM Bitcell Circuit Design with Virtual Ground Scheme

This paper presents new 8T SRAM design that avoids the stability and reliability issues of the conventional 6T and other existing SRAM cells. The proposed 8T SRAM is as good as the 10T design without the overheads of the 10T cell. In the proposed design, the virtual ground technique weakens the positive feedback and improves the writeability of the cell. The read operation does not require any precharging circuit leading to reduced area overheads for the SRAM memory system. The design isolates the storage node from the read path, which improves the read stability. For reliability study, we have investigated the static noise margin (SNM) of the proposed 8T SRAM and compared with the conventional designs at different process corners. The delay of the proposed bitcell is reduced to 69.67% during write and 52.87% during the read compared to conventional 6T bitcell. In addition to this, leakage currents of the proposed 8T bitcell reduced to 4.24%, 9.5% and 18.65% in the hold, read and write operations in contrast to conventional 6T bitcell. We have also analyzed the impact of the process and parametric variations in the proposed 8T SRAM using Monte Carlo simulations.