A Differential Single-Port 8T SRAM Bitcell for Variability Tolerance and Low Voltage Operation

被引：0

作者：

Ataei, Samira ^{[1
]}

Stine, James E. ^{[1
]}

机构：

[1] Oklahoma State Univ, VLSI Comp Architecture Res Grp, Dept Elect & Comp Engn, 202 Engn South, Stillwater, OK 74078 USA

来源：

2015 SIXTH INTERNATIONAL GREEN COMPUTING CONFERENCE AND SUSTAINABLE COMPUTING CONFERENCE (IGSC) | 2015年

关键词：

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

A novel single-port, fully differential 8-transistor (8T) SRAM bitcell that is tolerant to process variations and suitable for low-power operation is proposed in this paper. At 500mV supply voltage, the proposed 8T bitcell achieves 44% and 16% improvement in read Static Noise Margin (SNM) and Write Noise Margin (WNM), respectively, compared to the 6 Transistor (6T) bitcell. This 8T bitcell shows process variation tolerance which results in tight SNM and WNM distributions. It utilizes a differential operation, single read/write port and one wordline (WL), therefore, does not cause any changes in 6T SRAM architecture and can be used in current 6T memory compilers. The proposed 8T bitcell operates at a 500mV supply voltage with 130mV SNM and 220mV WNM. Simulation results with a an IBM cmos10lpe 65nm technology show this bitcell retains data at voltages down to 300 mV.

引用

页数：6

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