A Low Power AES-GCM Authenticated Encryption Core in 65nm SOTB CMOS Process

被引：0

作者：

Van-Phuc Hoang ^{[1
]}

Van-Tinh Nguyen ^{[1
]}

Anh-Thai Nguyen ^{[1
]}

Pham, Cong-Kha ^{[2
]}

机构：

[1] Le Quy Don Tech Univ, 236 Hoang Quoc Viet Str, Hanoi, Vietnam

[2] Univ Electrocommun, Grad Sch Informat & Engn, 1-5-1 Chofugaoka, Chofu, Tokyo 1828585, Japan

来源：

2017 IEEE 60TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS) | 2017年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a low power AES-GCM authenticated encryption IP core which combines an improved four-parallel architecture, an advanced 65nm SOTB CMOS technology and a low complexity clock gating technique. As a result, the power consumption of the proposed AES-GCM core is only 8.9mW which is lower than other AES-GCM IP cores presented in literature. The detail implementation results are also presented and discussed.

引用

页码：112 / 115

页数：4

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