A Low-Power mmWave CML Prescaler in 65nm SOI CMOS Technology

被引：0

作者：

Kim, Daeik D. ^{[1
]}

Cho, Choongyeun ^{[1
]}

Kim, Jonghae ^{[2
]}

Plouchart, Jean-Olivier ^{[3
]}

Lim, Daihyun ^{[4
]}

机构：

[1] IBM SRDC, Hopewell Jct, NY USA

[2] Qualcomm, San Diego, CA 92121 USA

[3] IBM Res, Yorktown Hts, NY 10598 USA

[4] MIT, Cambridge, MA 02139 USA

来源：

2008 IEEE CSIC SYMPOSIUM | 2008年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 5-stage CML prescaler operating up to 84GHz is presented. The prescaler requirements, design considerations, simulations, and performance measurements are presented. The first divide-by-2 stage consumes 17.7mW at 1.8V, or 26.4fJ power-delay product per gate. The prescaler's phase noise gain degeneration at the sensitivity curve boundary is reported for the first time.

引用

页码：178 / +

页数：2

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