Optimization and implementation on FPGA of the DCT/IDCT algorithm

被引：0
|
作者：
Ben Atitallah, A. [1 ]
Kadionik, P. [1 ]
Ghozzi, F. [1 ]
Nouel, P. [1 ]
Masmoudi, N. [1 ]
Marchegay, Ph. [1 ]
机构：
[1] Natl Engineers Sch Sfax ENIS, Lab Elect & Informat Technol, Sfax, Tunisia
来源：
2006 IEEE International Conference on Acoustics, Speech and Signal Processing, Vols 1-13 | 2006年
关键词：
D O I：
暂无
中图分类号：
O42 [声学];
学科分类号：
070206 ; 082403 ;
摘要：
this paper, we present a comparison between two methods, the modified Loeffler algorithm (11 MUL and 29 ADD) and Distributed Arithmetic, to implement the DCT/IDCT algorithm for MPEG or H.26x video compression using VHDL description language. The implementation has been achieved on Altera Stratix EP1S10 FPGA which provides a dedicated DSP blocks required for common signal processing functions. A new solution based on this DSP blocks used for to implement multipliers for the modified Loeffler algorithm in order to optimize speed and area.
引用
收藏
页码：3379 / 3382
页数：4
相关论文
共 50 条
  • [1] A fast algorithm of the DCT and IDCT for VLSI implementation
    Hong, Y
    Hou, ZH
    ICSP '96 - 1996 3RD INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING, PROCEEDINGS, VOLS I AND II, 1996, : 637 - 640
  • [2] Implementation of DCT and IDCT Based Image Compression and Decompression on FPGA
    Singh, Kamlesh Kumar
    Pandey, Deependra
    PROCEEDINGS OF THE 2017 INTERNATIONAL CONFERENCE ON INVENTIVE SYSTEMS AND CONTROL (ICISC 2017), 2017, : 803 - 806
  • [3] Design, optimisation and implementation of a DCT/IDCT-based image processing system on FPGA
    Tang, Shensheng
    Sinare, Monali
    Zheng, Yi
    INTERNATIONAL JOURNAL OF COMPUTER APPLICATIONS IN TECHNOLOGY, 2021, 67 (04) : 303 - 323
  • [4] On Hardware Implementation of DCT/IDCT for Image Processing
    Elhamzi, W.
    Saidani, T.
    Atri, M.
    Tourki, R.
    SCS: 2008 2ND INTERNATIONAL CONFERENCE ON SIGNALS, CIRCUITS AND SYSTEMS, 2008, : 316 - 319
  • [5] Techniques for efficient DCT/IDCT implementation on generic GPU
    Fang, B
    Shen, GB
    Li, SP
    Chen, HF
    2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 1126 - 1129
  • [6] The design and implementation of DCT/IDCT chip with novel architecture
    Cheng, KH
    Huang, CS
    Lin, CP
    ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL IV: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY, 2000, : 741 - 744
  • [7] An efficient method for hardware based DCT/IDCT implementation
    Sun, XT
    Wu, CK
    NEURAL NETWORK AND DISTRIBUTED PROCESSING, 2001, 4555 : 6 - 10
  • [8] A NOVEL 2-STAGE ALGORITHM FOR DCT AND IDCT
    WU, JL
    HSU, SH
    DUH, WJ
    IEEE TRANSACTIONS ON SIGNAL PROCESSING, 1992, 40 (06) : 1610 - 1612
  • [9] Implementation of DCT using variable iterations CORDIC algorithm on FPGA
    Mane, Mansi
    Patil, Dhanshree
    Sutaone, Mukul S.
    Sadalage, Akshay
    2014 First International Conference on Computational Systems and Communications (ICCSC), 2014, : 379 - 383
  • [10] AES Algorithm Optimization and FPGA Implementation
    Liu, Yufeng
    Xu, Xiangyang
    Su, Hao
    2019 3RD INTERNATIONAL WORKSHOP ON RENEWABLE ENERGY AND DEVELOPMENT (IWRED 2019), 2019, 267
12345