共 50 条
- [31] An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment Journal of Electronic Testing, 2002, 18 : 43 - 53
- [32] A low power deterministic test pattern generator for BIST based on cellular automata DELTA 2008: FOURTH IEEE INTERNATIONAL SYMPOSIUM ON ELECTRONIC DESIGN, TEST AND APPLICATIONS, PROCEEDINGS, 2008, : 266 - 269
- [33] X-Tolerant Tunable Compactor for In-System Test 2020 IEEE INTERNATIONAL TEST CONFERENCE (ITC), 2020,
- [34] Embedding a Low Power Test Set for Deterministic BIST using a Gray Counter WORLD CONGRESS ON ENGINEERING, WCE 2011, VOL II, 2011, : 1333 - 1338
- [36] Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST Journal of Electronic Testing, 2002, 18 : 159 - 170
- [38] Deterministic BIST with multiple scan chains Journal of Electronic Testing: Theory and Applications (JETTA), 1999, 14 (01): : 85 - 93
- [39] Deterministic BIST with multiple scan chains INTERNATIONAL TEST CONFERENCE 1998, PROCEEDINGS, 1998, : 1057 - 1064
- [40] Deterministic BIST in partial scan environment IMTC/O3: PROCEEDINGS OF THE 20TH IEEE INSTRUMENTATION AND MEASUREMENT TECHNOLOGY CONFERENCE, VOLS 1 AND 2, 2003, : 303 - 308