An effective design for hierarchical test generation based on strong testability

被引：0

作者：

Ichihara, H ^{[1
]}

Okamoto, N ^{[1
]}

Inoue, T ^{[1
]}

Hosokawa, T ^{[1
]}

Fujiwara, H ^{[1
]}

机构：

[1] Hiroshima City Univ, Grad Sch Informat Sci, Hiroshima, Japan

来源：

14TH ASIAN TEST SYMPOSIUM, PROCEEDINGS | 2005年

关键词：

hierarchical test generation; strong testability; datapath; test plan;

D O I：

10.1109/ATS.2005.23

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Hierarchical test generation is an efficient method of test generation for VLSI circuits. In this paper, we study a test plan generation algorithm for hierarchical test based on strong testability. We propose a heuristic algorithm for finding a control forest requiring a small number of hold functions by improving an existing test plan generation algorithm based on strong testability. Experimental results show that the proposed algorithm is effective in reducing additional hold functions, i.e., reducing hardware overhead and delay penalty of datapaths.

引用

页码：288 / 293

页数：6

共 50 条

[21] A low overhead design for testability and test generation technique for core-based systems-on-a-chip
Ghosh, I
Jha, NK
Dey, S
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1999, 18 (11) : 1661 - 1676
[22] Transparent DFT: A design for testability and test generation approach for synchronous sequential circuits
Pomeranz, Irith
Reddy, Sudhakar M.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2006, 25 (06) : 1170 - 1175
[23] Accurate testability analysis based-on multi-frequency test generation and a new testability metric
Abderrahman, A.
Savaria, Y.
Khouas, A.
Sawan, M.
2007 IEEE NORTH-EAST WORKSHOP ON CIRCUITS AND SYSTEMS, 2007, : 265 - 268
[24] DESIGN FOR TESTABILITY FOR COMPLETE TEST COVERAGE
MOTOHARA, A
FUJIWARA, H
IEEE DESIGN & TEST OF COMPUTERS, 1984, 1 (04): : 25 - 32
[25] Design for testability for in-circuit test
Johnson, Ken
Surface mount technology, 1990, 4 (02): : 23 - 26
[26] DESIGN FOR TESTABILITY WITH JTAG TEST METHODS
MCCLEAN, D
ROMEU, J
ELECTRONIC DESIGN, 1989, 37 (12) : 67 - &
[27] Design for testability of software-based self-test for processors
Nakazato, Masato
Ohtake, Satoshi
Inoue, Michiko
Fujiwara, Hideo
PROCEEDINGS OF THE 15TH ASIAN TEST SYMPOSIUM, 2006, : 375 - +
[28] FSMTEST - SYNTHESIS FOR TESTABILITY AND TEST-GENERATION OF PLA-BASED FSM
AVEDILLO, MJ
QUINTANA, JM
HUERTAS, JL
IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 1994, 141 (04): : 221 - 228
[29] Thermal Safe High Level Test Synthesis for Hierarchical Testability
Yeh, Tung-Hua
Wang, Sying-Jyan
2010 19TH IEEE ASIAN TEST SYMPOSIUM (ATS 2010), 2010, : 337 - 342
[30] TESTABILITY MEASURE TO IMPROVE ALGEBRAIC TEST GENERATION.
Lioy, Antonio
Mezzalama, Marco
Software & microsystems, 1984, 3 (02): : 37 - 41

← 1 2 3 4 5 →