Intrinsic Capacitance Extraction and Estimation for System-On-Chip Power Delivery Development

This paper presents the methodology of on-die parasitic intrinsic capacitance extraction and estimation at the early phase of system-on-chip (SOC) design and development cycle. Accurate estimation of the intrinsic capacitance is critical to prevent circuit overdesign and additional on-die decoupling capacitance requirements that could result in larger silicon footprint. The correlation of the simulated results and silicon measurement data is presented and further discussed in this study. Impacts of intrinsic capacitance to the power delivery capacitance and overall intellectual property (IP) block design optimization are also enveloped in this paper.