VLSI architecture for a flexible motion estimation with parameters

If motion estimation can choose the most suitable algorithm according to the changing characteristics of input image signals, we can get benefits, which improve quality and performance, reduce power consumption, and an optimize system. In this paper we propose a reconfigurable approach to motion estimation algorithm and architecture. The propose algorithm determines motion type and then selects adapted algorithm in order to improve quality and performance of images. We implemented the flexible and reconfigurable architecture by hardware with address generator unit, delay unit, and parameters. Our architecture supports more than one block-matching algorithm and parameters providing to optimize system. We are implementing our architecture by using hardware description language (VHDL) and synthesis design tools. We analyze the performance of architecture and present adaption to algorithm for a low cost real time application.